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? semiconductor msm56v16160d/dh 1/30 description the msm56v16160d/dh is a 2-bank 524,288-word 16-bit synchronous dynamic ram, fabricated in oki's cmos silicon-gate process technology. the device operates at 3.3 v. the inputs and outputs are lvttl compatible. features ? silicon gate, quadruple polysilicon cmos, 1-transistor memory cell ? 2-bank 524,288-word 16-bit configuration ? 3.3 v power supply, 0.3 v tolerance ? input : lvttl compatible ? output : lvttl compatible ? refresh : 4096 cycles/64 ms ? programmable data transfer mode C cas latency (1, 2, 3) C cas latency (2, 3)* 1 C burst length (1, 2, 4, 8, full page) C burst length (1, 2, 4, 8)* 1 C data scramble (sequential, interleave) * 1 : h version only. ? cbr auto-refresh, self-refresh capability ? package: 50-pin 400 mil plastic tsop (type ii) (tsopii50-p-400-0.80-k) (product : msm56v16160d/dh-xxts-k) xx indicates speed rank. product family ? semiconductor msm56v16160d/dh 2-bank 524,288-word 16-bit synchronous dynamic ram preliminary family access time (max.) msm56v16160d-10 msm56v16160d-12 msm56v16160dh-15 max. frequency 100 mhz 83 mhz 66 mhz 9 ns 10 ns 9 ns 9 ns 14 ns 9 ns t ac3 t ac2 this version: mar. 1998 e2g1049-18-33
? semiconductor msm56v16160d/dh 2/30 pin configuration (top view) v cc 1 v ss dq1 2 dq2 3 v ss q 4 dq3 5 dq4 6 v cc q 7 dq5 8 dq6 9 v ss q 10 dq7 11 dq8 12 v cc q 13 ldqm 14 we 15 cas 16 ras 17 cs 18 a11 19 a10 20 a0 21 a1 22 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 dq16 dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q nc udqm clk cke nc a9 a8 a7 a6 a2 23 a3 24 v cc 25 28 27 26 a5 a4 v ss 50-pin plastic tsop ( ii ) (k type) pin name function system clock clock enable address row address strobe column address strobe write enable data input/output mask data input/output power supply (3.3 v) ground (0 v) data output power supply (3.3 v) data output ground (0 v) clk cke a0 - a10 ras cas we udqm, ldqm dqi v cc v ss v cc q v ss q chip select cs bank select address a11 no connection nc pin name function note: the same power supply voltage must be provided to every v cc pin and v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin.
? semiconductor msm56v16160d/dh 3/30 pin description clk fetches all inputs at the "h" edge. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be masked so that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. row & column multiplexed. row address: ra0 C ra10 column address: ca0 C ca7 ras cas we functionality depends on the combination. for details, see the function truth table. udqm, ldqm masks the read data of two clocks later when udqm and ldqm are set "h" at the "h" edge of the clock signal. masks the write data of the same clock when udqm and ldqm are set "h" at the "h" edge of the clock signal. udqm controls upper byte and ldqm controls lower byte. address dqi data inputs/outputs are multiplexed on the same pin. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke, udqm and ldqm. selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. a11 = "l" : bank a, a11 = "h" : bank b a11
? semiconductor msm56v16160d/dh 4/30 block diagram timing register progra- ming register latency & burst controller cke clk cs ras cas we internal col. address counter column address buffers internal row address counter row address buffers a0 - a11 8 12 row decoders word drivers 8mb memory cells 12 8 column decoders sense amplifier 16 read data register output buffers input data register input buffers 16 dq1 - dq16 i/o controller 16 udqm bank controller a11 row decoders word drivers 8mb memory cells sense amplifier column decoders 16 16 ldqm
? semiconductor msm56v16160d/dh 5/30 electrical characteristics absolute maximum ratings (voltages referenced to v ss ) parameter unit symbol voltage on any pin relative to v ss rating v in , v out C0.5 to v cc + 0.5 v v cc supply voltage v cc , v cc q C0.5 to 4.6 v storage temperature t stg C55 to 150 c power dissipation p d * 600 mw short circuit current i os 50 ma operating temperature t opr 0 to 70 c *: ta = 25 c (voltages referenced to v ss = 0 v) parameter unit symbol power supply voltage v cc , v cc q input high voltage v ih input low voltage v il min. 3.0 2.0 C0.3 v v v typ. 3.3 max. 3.6 v cc + 0.2 0.8 recommended operating conditions capacitance (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) parameter unit symbol input capacitance (clk, cke, cs , ras , cas , we , udqm, ldqm) input/output capacitance (dq1 - dq16) c in2 c out 2 2 pf pf input capacitance (a0 - a11) c in1 2pf 5 5 7 min. max.
? semiconductor msm56v16160d/dh 6/30 dc characteristics parameter condition version unit note cke others bank d-10 d-12 dh-15 symbol output high voltage output low voltage input leakage current 2.4 C 10 v v m a i oh = C2 ma i ol = 2 ma v oh v ol i li 0.4 10 2.4 C 10 0.4 10 2.4 C 10 0.4 10 output leakage current C 10 m a i lo 10 C 10 10 C 10 10 min. max. min. max. min. max. average power supply current (operating) ma 1, 2 cke 3 v ih t cc = min t rc = min no burst one bank active i cc 1 80 70 60 ma 1, 2 cke 3 v ih t cc = min t rc = min t rrd = min no burst both banks active i cc 1d 115 95 80 power supply current (stand by) ma 3 cke 3 v ih t cc = min both banks precharge i cc 2 35 30 25 average power supply current (clock suspension) ma 2 cke v il t cc = min both banks active i cc 3s 3 3 3 power supply current (burst) ma 1, 2 cke 3 v ih t cc = min both banks active i cc 4 100 85 70 power supply current (auto-refresh) ma 2 cke 3 v ih t cc = min t rc = min one bank active i cc 5 80 70 60 average power supply current (self-refresh) ma cke v il t cc = min both banks precharge i cc 6 2 2 2 average power supply current (power down) ma cke v il t cc = min both banks precharge i cc 7 2 2 2 average power supply current (active stand by) ma 3 cke 3 v ih t cc = min one bank active i cc 3 40 35 30 notes: 1. measured with outputs open. 2. the address and data can be changed once or left unchanged during one cycle. 3. the address and data can be changed once or left unchanged during two cycles.
? semiconductor msm56v16160d/dh 7/30 mode set address keys a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 cas latency burst type burst length 000 reserved 0 sequential 000 1 1 001 1 interleave 001 2 2 010 010 4 4 011 011 8 8 1 * 2 2 3 100 reserved 100 reserved reserved 101 reserved 101 reserved reserved 110 reserved 110 reserved reserved 111 reserved 111 full page * 2 reserved * 2 : not applicable to h version. note: a7, a8, a9, a10 and a11 should stay "l" during mode set cycle. power on sequence 1. with inputs in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 m s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply a cbr auto-refresh eight or more times. 5. enter the mode register setting command.
? semiconductor msm56v16160d/dh 8/30 ac characteristics parameter msm56v16160d-10 msm56v16160d-12 msm56v16160dh-15 clock cycles time access time from clock clock "h" pulse time clock "l" pulse time input setup time input hold time output low impedance time from clock output high impedance time from clock output hold from clock ras cycle time ras precharge time ras active time write recovery time write command input time from output refresh time power-down exit set-up time ras to cas delay time cl = 3 cl = 2 cl = 1 cl = 3 cl = 2 cl = 1 symbol t cc t ch t cl t si t hi t rc t rp t ras t wr t ref t pde t rcd t olz t ohz min. 10 15 30 3 3 3 1 100 30 60 15 t si + 1 clk 30 3 max. 9 9 27 10 5 64 8 min. 12 17.5 35 3 3 3 1 115 35 70 24 t si + 1 clk 35 3 max. 10 14 30 10 5 64 10 min. 15 15 3 3 3 1 105 30 70 15 t si + 1 clk 30 3 max. 9 9 10 5 64 8 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns note 3, 4 3, 4 3, 4 l owd 2 2 2 cycle ras to ras bank active delay time t rrd 20 24 24 ns input level transition time t t 333ns t oh 3 3 3 ns 3 cas to cas delay time (min.) l ccd 1 1 1 cycle 111 clock disable time from cke l cke cycle 222 data output high impedance time from udqm, ldqm l doz cycle 000 data input mask time from udqm, ldqm l dod cycle 000 data input time from write command l dwd cycle data output high impedance time from precharge command l roh 1 1 cycle 2 2 2 cycle cl = 1 cl > 1 333 active command input time from mode register set command input (min.) l mrd cycle note 1, 2 t ac
? semiconductor msm56v16160d/dh 9/30 notes : 1. ac measurements assume that t t = 1 ns and v ih /v il = 2.0 v/0.8 v. 2. the reference level for timing of input signals is 1.4 v. 3. output load. output z = 50 w 50 pf 50 w 1.4 v 4. the access time is defined at 1.4 v. 5. if t t is longer than 1 ns, then the reference level for timing of input signals is v ih and v il .
? semiconductor msm56v16160d/dh 10/30 timing waveform read & write cycle (same bank) @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm qa0 t oh t rc cs t rp t rcd a11 a10 qa1 qa2 qa3 db0 db1 db2 db3 t ohz row active read command precharge command row active write command precharge command ra rb t wr t ac ra ca0 rb cb0
? semiconductor msm56v16160d/dh 11/30 single bit read-write-read cycle (same page) @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm ra ca qa cs a11 a10 cb cc db qc row active read command read command write command precharge command t ch t cc t cl t si t hi t si t hi t si l ccd t hi t si bs bs bs bs t si t hi bs ra t hi t si t ac t olz t ohz t hi t si t oh high l owd
? semiconductor msm56v16160d/dh 12/30 * notes: 1. when cs is set "high" at a clock transition from "low" to "high", all inputs except cke, udqm, and ldqm are invalid. 2. when issuing an active, read or write command, the bank is selected by a11. 3. the auto precharge function is enabled or disabled by the a10 input when the read or write command is issued. a11 0 1 active, read or write bank a bank b a10 0 operation after the end of burst, bank a holds the idle status. a11 0 0 0 after the end of burst, bank b holds the idle status. 1 1 after the end of burst, bank a is precharged automatically. after the end of burst, bank b is precharged automatically. 1 1 4. when issuing a precharge command, the bank to be precharged is selected by the a10 and a11 inputs. a10 0 0 1 a11 0 1 x operation bank a is precharged. bank b is precharged. both banks a and b are precharged. 5. the input data and the write command are latched by the same clock (write latency = 0). 6. the output is forced to high impedance by (1 clk + t ohz ) after udqm, ldqm entry.
? semiconductor msm56v16160d/dh 13/30 page read & write cycle (same bank) @ cas latency = 2, burst length = 4 * notes: 1. to write data before a burst read ends, udqm and ldqm should be asserted three cycles prior to the write command to avoid bus contention. 2. to assert row precharge before a burst write ends, wait t wr after the last write data input. input data during the precharge input cycle will be masked internally. clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm ca0 cb0 cs a11 a10 cc0 cd0 read command write command precharge command bank a active read command write command high l ccd *note1 qa0 t wr qa1 qb0 qb1 dc0 dc1 dd0 *note2 l owd
? semiconductor msm56v16160d/dh 14/30 read & write cycle with auto precharge @ burst length = 4 clk 012345678910111213141516171819 cke ras cas addr we dq udqm, ldqm cs a11 a10 qa0 row active (a-bank) row active (b-bank) a-bank precharge start b bank write with auto precharge cas latency = 1 *note1 udqm, ldqm dq cas latency = 2 dq udqm, ldqm cas latency = 3 qa1 qa2 qa3 db0 db1 db2 db3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 a bank read with auto precharge b bank precharge start point high a-bank precharge start a-bank precharge start t wr ra rb ra rb ca cb t rrd * note: 1. not applicable to h version.
? semiconductor msm56v16160d/dh 15/30 bank interleave random row read cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm cs a11 a10 qaa0 row active (a-bank) row active (a-bank) read command (b-bank) precharge command (b-bank) t rc raa t rrd rbb rac qaa1 qaa2 qaa3 qbb1 qbb2 qbb3 qbb4 qac0 qac1 qac2 read command (a-bank) row active (b-bank) precharge command (a-bank) read command (a-bank) high qac3 raa caa rbb cbb rac cac
? semiconductor msm56v16160d/dh 16/30 bank interleave random row write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm cs a11 a10 daa0 row active (a-bank) precharge command (a-bank) raa daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 write command (a-bank) row active (b-bank) rac rbb write command (b-bank) precharge command (a-bank) row active (a-bank) precharge command ( b-bank ) write command (a-bank) high raa caa rbb cbb rac ca
? semiconductor msm56v16160d/dh 17/30 bank interleave page read cycle @ cas latency = 2, burst length = 4 *note: 1. cs is ignored when ras , cas and we are high at the same cycle. clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm cs a11 a10 qaa0 row active (a-bank) read command (a-bank) raa qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qae0 qae1 read command (a-bank) row active (b-bank) raa read command (b-bank) read command (a-bank) read command (b-bank) qac0 qac1 qbd0 qbd1 precharge command (a-bank) high l roh *note1 raa caa rbb cbb cac cbd cae
? semiconductor msm56v16160d/dh 18/30 bank interleave page write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm cs a11 a10 daa0 row active (a-bank) precharge command ( both bank ) raa daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 write command ( a-bank ) row active (b-bank) rab write command ( b-bank ) write command ( a-bank ) write command (b-bank) dbd0 high raa caa rbb cbb cac cbd
? semiconductor msm56v16160d/dh 19/30 bank interleave random row read/write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm raa caa cs a11 a10 qaa0 row active (a-bank) raa rbb cbb rac qaa1 qaa2 qaa3 read command ( a-bank ) row active (b-bank) precharge command ( a-bank ) cac rac rbb dbb0 dbb1 dbb2 dbb3 qac0 qac1 qac2 qac3 write command (b-bank) row active ( a-bank ) read command (a-bank) high
? semiconductor msm56v16160d/dh 20/30 bank interleave page read/write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm caa0 cs cbb0 cac0 a11 a10 high read command (a-bank) write command (b-bank) read command (a-bank) qac3 dbb3 qaa3 qaa2 qaa1 qaa0 dbb2 dbb1 dbb0 qac2 qac1 qac0
? semiconductor msm56v16160d/dh 21/30 clock suspension & dqm operation cycle @ cas latency = 2, burst length = 4 *notes: 1. when clock suspension is asserted, the next clock cycle is ignored. 2. when ldqm and udqm are asserted, the read data after two clock cycles is masked. 3. when ldqm and udqm are asserted, the write data in the same clock cycle is masked. 4. when ldqm is set high, the input/output data of dq0 - dq7 is masked. when udqm is set high, the input/output data of dq8 - dq15 is masked. clock suspension clk 012345678910111213141516171819 cke ras cas addr dq0 - 7 we udqm ra cs ca cb a11 a10 row active qb1 qb0 read command read command read dqm write command clock suspension write dqm read dqm cc t ohz dc2 dc0 qa1 qa0 qa2 t ohz write dqm *note1 ? *note1 *note4 qb1 qb0 dc1 dc0 qa2 dq8 - 15 ldqm *note4 qa0 qa3 *note2 *note3 ? read dqm ra
? semiconductor msm56v16160d/dh 22/30 read to write cycle (same bank) @ cas latency = 2, burst length = 4 clk cke ras cas addr dq we cs a11 a10 012345678910111213141516171819 da0 t rcd da1 da2 da3 row active read command write command precharge command ra t wr ra ca0 *note1 ca0 udqm, ldqm *note: 1. in case cas latency is 3, read can be interrupted by write. the minimum command interval is [burst length + 1] cycles. udqm, ldqm must be high at least 3 clocks prior to the write command.
? semiconductor msm56v16160d/dh 23/30 read interruption by precharge command @ burst length = 8 *notes: 1. when the cas latency = 1, and if row precharge is asserted before a burst read ends, then the read data will not output after the next clock cycle of the precharge command. 2. when the cas latency = 2 or 3, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 3. not applicable to h version. we clk 012345678910111213141516171819 cke ras cas addr dq udqm, ldqm cs ca a11 a10 high row active read command precharge command qa3 qa2 qa1 qa0 dq udqm, ldqm udqm, ldqm cas latency = 1 *note3 dq cas latency = 3 cas latency = 2 qa4 qa3 qa2 qa1 qa0 qa4 qa3 qa2 qa1 qa0 qa4 ra qa5 qa5 *note1 *note2 *note2 ra
? semiconductor msm56v16160d/dh 24/30 power down mode @ cas latency = 2, burst length = 4 *notes: 1. when both banks are in precharge state, and if cke is set low, then the msm56v16160d/dh enters power-down mode and maintains the mode while cke is low. 2. to release the circuit from power-down mode, cke has to be set high for longer than t pde (t si + 1 clk). clock suspention exit clk 012345678910111213141516171819 cke ras cas addr dq we udqm, ldqm cs a11 a10 qa2 qa1 qa0 t si t pde t si t si ra ca row active power-down entry power-down exit clock suspention entry read command precharge command *note1 *note2 ra
? semiconductor msm56v16160d/dh 25/30 self refresh cycle clk 012 cke ras cas addr dq we udqm, ldqm cs a11 a10 t si t rc hi - z hi - z self refresh entry self refresh exit row active ra ra bs
? semiconductor msm56v16160d/dh 26/30 mode register set cycle clk 012345 012345678910 cke ras cas addr dq we udqm, ldqm cs key ra mrs high high hi - z hi - z new command auto refresh t rc 6 11 12 l mrd auto refresh auto refresh cycle
? semiconductor msm56v16160d/dh 27/30 function truth table (table 1) (1/2) current state 1 cs ras cas we ba addr hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllhx x hxxxx x lhhxx x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 lhllx x l l h x ba ra, a10 lllxx x idle row active read write read with auto precharge hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 lhllx x l l h x ba ra, a10 lllxx x write with auto precharge action nop nop illegal 2 illegal 2 row active nop 4 auto-refresh or self-refresh 5 nop nop read write illegal 2 precharge illegal nop (continue row active after burst ends) nop (continue row active after burst ends) reserved term burst, start new burst read term burst, start new burst write illegal 2 term burst, execute row precharge illegal nop (continue row active after burst ends) nop (continue row active after burst ends) illegal 2 term burst, start new burst read term burst, start new burst write illegal 2 term burst, execute row precharge illegal nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal 2 illegal 2 illegal illegal 2 illegal nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal 2 illegal 2 illegal illegal 2 lllxx x illegal lllllop code mode register write
? semiconductor msm56v16160d/dh 28/30 function truth table (table 1) (2/2) notes: 1. all inputs are enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of t ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle. current state 1 cs ras cas we ba addr hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhxx x lhlxx x llhxx x lllxx x hxxxx x lhhhx x lhhlx x lhlxx x llxxx x precharge write recovery row active refresh mode register access action nop --> idle after t rp nop --> idle after t rp illegal 2 illegal 2 illegal 2 nop 4 illegal nop nop illegal 2 illegal 2 illegal 2 illegal 2 illegal nop --> row active after t rcd nop --> row active after t rcd illegal 2 illegal 2 illegal 2 illegal 2 illegal nop --> idle after t rc nop --> idle after t rc illegal illegal illegal nop nop illegal illegal illegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge
? semiconductor msm56v16160d/dh 29/30 current state (n) cken-1 cs ras cas we addr h xxxx x l hxxx x l lhhh x llhhlx llhlxx lllxxx l xxxx x h xxxx x l hxxx x l lhhh x llhhlx llhlxx lllxxx l xxxx x h xxxx x h hxxx x h lhhh x hlhhlx hlhlxx hllhlx h lllh x h xxxx x h xxxx x l xxxx x l xxxx x self refresh power down all banks idle 6 any state other action invalid exit self refresh --> abi exit self refresh --> abi illegal illegal illegal nop (maintain self refresh) invalid exit power down --> abi exit power down --> abi illegal illegal illegal 6 nop (continue power down mode) refer to table 1 enter power down enter power down illegal illegal illegal enter self refresh refer to operations in table 1 begin clock suspend next cycle enable clock of next cycle continue clock suspension cken x h h h h h l x h h h h h l h l l l l l l h l h l (abi) than listed above h llll x illegal l l xxxx x nop l function truth table for cke (table 2) note: 6. power-down and self refresh can be entered only when all the banks are in an idle state.
? semiconductor msm56v16160d/dh 30/30 package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit : mm) tsop ii 50-p-400-0.80-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.61 typ. mirror finish

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